MemryX Targets 10x Compute Jump With MX3+ Edge AI Chip

MemryX has announced the MX3+ inference accelerator with design targets of up to 10 times more peak AI compute and nearly 10 times more on-chip memory than its current MX3 chip — while staying inside the same low-power operating envelope. The company announced the product on November 10, 2026. Every performance figure in the announcement is a design target, not a measured result, and volume production is not planned until mid-2028.

The Ann Arbor fabless semiconductor company (a chip designer that outsources manufacturing) is aiming the device at edge hardware, industrial systems and high-density inference infrastructure running larger or more complex models. The stakes are straightforward: edge deployments face rigid board-space, system-cost and power constraints that datacenter hardware does not, and model sizes keep growing. A chip that holds more model weights on-die without raising power draw would let robotics, industrial automation and video systems run transformer-class networks locally rather than in the cloud.

What exactly is being promised?

The headline numbers describe a future product. According to MemryX's MX3+ product page, the design retains MX3's silicon footprint while providing 10 times more model-weight capacity, addressing board-space and system-cost constraints as well as power. That is the central engineering constraint: increase compute and model storage substantially without expanding the power or physical budget that shaped the predecessor.

For reference, the current MX3 is available for volume orders today. MemryX lists it at 6.25 TFLOPS of AI compute and 10.5 MB of on-chip weight memory per chip, with power consumption spanning 200 mW to 3 W. If MX3+ hits its targets, it would deliver roughly an order of magnitude more compute and memory per chip within that same 200 mW-to-3 W envelope. MemryX has not yet disclosed the absolute TFLOPS or memory figures for MX3+ in this announcement — only the multipliers and the 16-chip configuration totals.

Planned workloads include:

• Higher-resolution vision
• Transformer-based models
• Small language models (compact text-generation models sized for edge hardware)
• Vision-language-action models
• Hybrid architectures and more sophisticated multi-model pipelines

Target deployments span industrial automation, robotics, intelligent transportation, smart infrastructure, video management, healthcare devices, retail and consumer electronics. That list is broad, and MemryX has not said which segments it expects first.

How does multi-chip scaling work?

Planned configurations will scale from one MX3+ to 16 chips operating as a unified logical device. MemryX says the 16-chip configuration is designed to deliver more than 1 POPS — one peta-operation per second — of peak AI compute and 2.16 GB of distributed on-chip memory.

The mechanism is distributed dataflow, an approach that lets the accelerators work together without requiring the host processor to manage individual chips. The MemryX Neural Compiler automatically maps neural networks across the available accelerators, so developers can scale performance without manually partitioning their models. Manual partitioning is a common cost in multi-chip edge systems, so compiler-led mapping is the claim doing the heavy lifting here.

MX3+ combines the additional on-chip memory with near-memory, pipelined processing that keeps model data close to computation, minimizing data movement. The design targets larger models and higher-resolution inputs while maintaining predictable, low-latency inference at batch size one (processing one input at a time rather than batching, which is the norm in real-time edge applications).

The scaling architecture is not new. The existing MX3 datasheet documents the same ceiling: host offload over PCIe or USB, support for x86, Arm and RISC-V processors, and PCIe cascading of up to 16 chips through a single host interface. MX3+ retains that multi-chip approach and a familiar development workflow as models and systems become more complex.

President and CEO Ross Jatou framed the value proposition around continuity rather than raw speed. MemryX expects the shared architecture to provide one development-to-production path across embedded, industrial and high-density systems and to significantly lower total cost of ownership for high-density edge deployments, Jatou said. Total cost of ownership is a reasonable metric for a product whose per-chip price MemryX has not announced.

When will hardware actually exist?

Not soon. MemryX is accepting early-access requests from selected strategic partners and enterprise customers to co-validate pre-production hardware and software. The company targets engineering samples for late 2027 and volume production for mid-2028, with further specifications, configurations and availability information to come as development progresses.

That timeline means roughly 20 months separate the announcement from engineering samples. In the edge AI market, where competitors iterate annually, MemryX is asking customers to plan around targets that remain unvalidated until pre-production silicon runs.

The immediate work is validation rather than deployment. Early-access systems will need to show that the compute and memory gains can coexist with MX3's power and footprint constraints while preserving compiler-led scaling and predictable low-latency inference. Ten-fold jumps in two dimensions while holding a third constant is the kind of claim that silicon physics, not marketing, will adjudicate.

What comes after MX3+?

MemryX says new capabilities in MX3+ will carry into MX4, its future platform for advanced multimodal and large-language-model inference. The official MX4 product page adds advanced vision and generative AI to its target workloads and targets availability in 2029.

The roadmap signals MemryX's ambition to move from vision-centric edge inference toward large language models at the edge — a market where on-chip memory capacity, exactly the resource MX3+ claims to multiply tenfold, is the binding constraint. Whether the 2028 silicon validates the 2026 targets will determine whether that roadmap reads as a plan or a wish.

By James Calloway