Luminal raises $25M Series A to make AI chips do more work

Luminal has raised a $25 million Series A led by Standard Capital, the investor announced on November 12, 2026. The AI infrastructure startup sells a compiler and a hosted inference service built around a single idea: extracting more useful work from hardware customers already own.

The round follows a $5.3 million seed announced on November 17, 2025, led by Felicis Ventures with angel investors including Paul Graham and Guillermo Rauch. Co-founders Joe Fioti, Jake Stevens and Matthew Gunton now have the capital to push deeper into a market where inference — the computation that produces an AI model's output — has become the dominant cost of running AI at scale.

What does Luminal actually build?

Luminal runs two businesses around inference. It hosts models on its own cloud, Luminal Cloud, and it licenses its compiler to customers that already operate their own hardware. That split gives the company a managed service for customers that want deployment handled and a separate product for organizations trying to improve their own infrastructure.

The compiler itself sits at the technical core. A compiler translates a model written in a framework such as PyTorch into the low-level code that executes its mathematical operations. Luminal's technical overview describes a pipeline that lowers a model into a dataflow graph, applies hardware-aware fusion, tiling, memory planning and scheduling, and then emits GPU kernels or instructions for application-specific integrated circuits. Compiling ahead of execution reduces the runtime overhead of interpreting a model dynamically.

The distinctive part is how the compiler finds fast implementations. Luminal spends substantial computation during compilation to search possible implementations rather than relying only on handwritten heuristics, the founders said. The technique, equality saturation, compactly represents a search space that can contain trillions of options on a given chip, letting the compiler search for an optimized version. The founders' bet is that this matters more as processors get more specialized, requiring more complex memory and scheduling decisions in software.

In short: Luminal trades compute time at compile time for speed at run time.

How fast is it?

The company's numbers come from its own website's comparison. Luminal reports 36,000 tokens per second for GPT-OSS 120B on eight Nvidia H100 SXM GPUs, compared with 28,000 for TensorRT-LLM and 26,000 for vLLM.

A January 9, 2026 technical post explains one mechanism behind those figures: automatically generated megakernels. Fusing a model's forward pass into one kernel — a single GPU program — removes repeated kernel-launch delays and lets later operations begin as soon as their input data is ready. The design also targets idle periods caused by uneven work across processor cores and waits for initial weights to load, using fine-grained synchronization to preserve data dependencies.

Those results anchor the commercial pitch: if the same GPUs produce more tokens per second, the effective cost of every request drops.

Who's using it?

Two customers illustrate the range of production traffic. Real-estate media company AutoHDR processes about 5 million images a month, and Luminal handles almost all of that workload while moving a growing share onto AMD chips, the founders said. Another customer, Freebuff, sends Luminal trillions of tokens each week.

The Freebuff workload highlights a cost problem that a fast kernel alone doesn't solve. In the founders' account, Freebuff's coding requests can contain on the order of 100,000 input tokens, making cache-hit rates and request scaling important costs. Reusing cached computation avoids running it again, and moving relevant caches through the memory hierarchy helps preserve that saving.

So Luminal's inference layer does more than compile code. Above the compiler, it schedules and balances work across CPUs, GPUs and ASICs, redistributes tasks as utilization changes and starts or stops nodes with demand. On the hosted side, Luminal Cloud provides managed serverless endpoints, automatic batching and scale-to-zero capacity, with customers paying for what they use.

How does the pricing work?

For some compiler licenses, Fioti described pricing as a fixed fraction of the measured improvement over a customer's existing baseline. His illustrative example: doubling throughput on a GPU costing $1.50 saves 75 cents; Luminal charges 25 cents and leaves the customer with a 50-cent saving.

That structure ties license revenue to the value delivered rather than to hosted usage alone. It also lowers the barrier for customers with sunk hardware costs — they pay only when the compiler demonstrably beats what they already run.

Why did open source lead here?

Luminal began as a side project Fioti developed outside his job to run models on a laptop. The project later added an Nvidia backend and built an open-source community. The founders settled on keeping the core compiler open while charging for hosting, a model they compared with Vercel's pairing of Next.js and its cloud.

The compiler license adds a second route for organizations whose hardware is already in place. Open source builds trust with engineers; the hosted cloud and the value-based license convert that trust into revenue.

The takeaway: Luminal is following a well-worn open-core playbook, but pointing it at compilers rather than web frameworks.

What comes next?

Luminal is now recruiting compiler engineers and its first non-engineering employee, a head of growth. The team works in person in downtown San Francisco and has so far been engineering-only. The immediate hiring plan points to deeper compiler expertise and a first commercial function.

The founders expect inference workloads to be divided increasingly between chips specialized for prompt processing and those specialized for token generation. That split makes coordination across hardware types a larger software challenge.

The broader test is whether Luminal can preserve its reported cost advantages as inference spreads across chips designed for different stages of a request, where scheduling and cache reuse become part of the savings calculation alongside raw compiler performance.