Expedera, Cadence report validated pre-silicon edge AI integration

On November 9, 2026, Expedera announced a pre-silicon integration of its Origin Evolution neural processing unit (NPU) IP with Cadence’s Tensilica NeuroEdge 130 AI Co-Processor, describing the simulation as validated. In the simulation, the two semiconductor IP blocks divided and executed AI inference workloads.

Expedera did not call the result a customer-silicon benchmark, and neither Expedera nor Cadence published combined performance or power-efficiency measurements.

Expedera’s announcement included no joint figures for latency, cost or design complexity, even though those were design goals for the combined subsystem. Expedera and Cadence designed it to improve performance and power efficiency while reducing latency, cost and complexity.

Expedera and Cadence target inference designs across edge nodes, smartphones, automotive systems and data centers. The approach can extend to other Tensilica digital signal processors.

For edge system-on-chip designers, the partnership matters because it joins two existing IP families before a customer-silicon benchmark. Expedera’s announcement frames the subsystem as a way to balance specialized neural acceleration with programmable handling of surrounding operators and unforeseen workloads.

Expedera chief scientist Sharad Chole said models run on the combined subsystem. He also said agentic AI workflows help Expedera deliver customized IP more quickly. Chole said the project should give customers “a faster, lower-risk path to production edge AI tailored to their performance and power requirements.”

How do the two IP blocks divide inference work?

Amol Borkar, group director of product management and marketing for Cadence’s Tensilica Products Group, said NeuroEdge 130 assists Origin Evolution with pre-processing and post-processing. The co-processor also provides operator fallback and executes AI networks. Borkar described a division of labor instead of assigning identical tasks to both accelerators.

In Borkar’s account, the split gives Expedera’s packet-based NPU the network-processing role and Cadence’s co-processor the surrounding work. Programmable instructions let the co-processor cover operations that do not suit a fixed NPU path.

According to Cadence, NeuroEdge 130 was designed to work alongside Cadence’s Neo NPUs, customer-developed NPUs or third-party NPU IP. The Expedera collaboration demonstrates the third-party route.

Cadence’s product documentation describes an Xtensa-based architecture using very long instruction word (VLIW) and single instruction, multiple data (SIMD) techniques. Cadence added optimized instructions for sigmoid, tanh and ReLU operations, which its documentation identifies as less suited to NPUs.

The co-processor can also serve as a control processor. According to Cadence, it can issue instructions and commands to an NPU, adding programmability for workloads that were not anticipated when the subsystem was designed.

Cadence says NeuroEdge 130 connects through AXI or its High Bandwidth Direct Interface. Its NeuroWeave software development kit, built on the Tensor Virtual Machine stack, tunes, optimizes and deploys models on Cadence AI IP.

What can Origin Evolution handle?

Origin Evolution debuted on May 20, 2025 as available, production-ready and silicon-proven in customer production designs. That status applies to the NPU independently of the November 2026 simulation with Cadence.

Expedera builds Origin Evolution around packets, which the company defines as contiguous fragments of neural networks. The NPU routes those packets through Feed Forward, Attention and Vector processing blocks.

• The three blocks handle varying operations, data types and precisions, according to Expedera.
• Origin Evolution supports LLMs, CNNs, RNNs, and custom or black-box layers.
• Expedera says the packet design is intended to reduce large memory movements while allowing different kinds of network work to share one architecture.

Expedera’s May 2025 launch put a production-ready NPU on one side of the pairing. Cadence’s May 2025 launch put a generally available, ISO 26262-ready co-processor on the other. The November 2026 work tests their interoperability, not either product’s standalone maturity.

Both IP blocks already had standalone launch dates before the pairing. Expedera’s announcement presents the November 2026 result as a test of their combined operation, not a launch of either product.

What do the earlier product figures prove?

Origin Evolution’s launch figures apply to the NPU alone. Expedera reports scalability to 128 TFLOPS in one core and to petaFLOPS and beyond with multiple cores. The company also reports more than a 75% reduction in external memory moves for Llama 3.2 1B and Qwen2 1.5B compared with alternative solutions.

Cadence introduced NeuroEdge 130 on May 7, 2025. The co-processor reached general availability and ISO 26262-ready status for automotive applications. Cadence reported more than 30% area savings and over 20% lower dynamic power and energy at comparable performance to Tensilica Vision DSPs on AI networks and operators.

Expedera’s announcement separates NeuroEdge 130’s standalone Vision DSP comparison from the new subsystem. The comparison does not establish what the Expedera-Cadence subsystem would save in area, consume in power or deliver in performance. Expedera and Cadence published no combined figures for any of those results.

Neither set of standalone numbers can be added to the other. Expedera and Cadence did not publish combined measurements for better performance, lower power use, reduced latency, lower cost or lower complexity.

Why does the integration matter for edge chips?

The integration is a production-engineering exercise, not a contest between the two accelerators. According to Expedera and Cadence, it provides a validated path between Expedera’s packet-based acceleration and Cadence’s programmable handling of surrounding operators and unforeseen workloads.

Expedera and Cadence identify a practical tension between dense network math, which benefits from specialized acceleration, and changing models, which require programmability. Origin Evolution takes the specialized path through its Feed Forward, Attention and Vector blocks. NeuroEdge 130 handles pre-processing, post-processing and fallback, and it can command the NPU for work not anticipated at design time.

Designers can configure the subsystem for different performance and power targets, according to Expedera and Cadence. The approach can also extend to other Tensilica digital signal processors.

For now, the engineering claim is interoperability. Expedera says models run on the combined subsystem, and Chole says agentic AI workflows are shortening the path to customized production IP. The performance claims remain untested in customer silicon.

The next evidentiary milestone is a customer-silicon build with joint measurements of performance, power, latency and cost. Until then, the November 9 simulation shows that two existing IP blocks can divide inference work, not that their combination beats competing edge-AI subsystems.